The purpose of this workshop is to bring researchers and practitioners of LSI testing from all over the world together to exchange ideas and experiences in register transfer level (RTL), high level and system level testing. WRTLT’16, the seventeenth workshop, will be held in conjunction with the 25th Asian Test Symposium (ATS’16) in Hiroshima, Japan. We hope and expect this workshop provides an ideal forum for frank discussion on this important topic for the future system-on-a-chip (SoC) devices.
Areas of interest include but not limited to:
RTL fault modeling, ATPG, DFT, BIST
High-level fault modeling, testing and synthesis for testability
Functional fault modeling and test bench generation
3D IC testing
SoC/NoC testing, test scheduling, core-based testing, interconnect testing
Reliable SoC, system level reliability, self repair, fault tolerant SoC
Microprocessor testing, design verification
11月24日
2016
11月25日
2016
初稿截稿日期
终稿截稿日期
注册截止日期
2017年11月30日 台湾-中国
2017年 RTL和高级测试研讨会
留言