VARI 2016 is the 7th International Workshop on CMOS Variability. The increasing variability in CMOS transistor characteristics, as well as its sensitivity to environmental variations has become a major challenge to scaling and integration. Strong links must be established between circuit design, system design and device technology. The VARI workshop answers to the need to have an event on variability in CMOS technology development and circuit design, where industry and academia meet. VARI objective is to provide a forum to discuss and investigate the CMOS process and environmental variability issues in methodologies and tools for the design of integrated circuits and systems. The program will focus on performance and power consumption as well as architectural aspects like adaptability or resilience, with particular emphasis on modeling, design, characterization, analysis and optimization in respect to variability. Digital, Analog, Mixed Signal and RF circuits are within VARI scope.
Topics of Interest:
Papers are solicited on, but not limited to, the following topics:
Timing and Performance
Methodologies and tools for the analysis, design and verification of timing and performance properties of integrated circuits and systems at all levels of abstraction;
Design for yield, design for manufacturability;
Simulation tools;
Design and issues concerning asynchronous systems;
Special timing or performance related topics, e.g. synchronization, side-channel attacks.
Coupling efffects: analysis, modelling, simulation & experimentation
Low Power and Thermal-aware Design
Design techniques for thermal-aware and low power circuits and systems
Power/thermal-aware synthesis and floorplanning
Policies for power and thermal optimization
Power/Thermal Estimation and Optimization
Power/Thermal-aware architectures
Hardware-software interaction for power/temperature minimization
Energy-harvesting
Low Power Systems: wireless sensor networks, mobile computing
Compilers, operating systems and runtime systems
Power efficiency through parallelizing compilers or parallel programming
Concepts for programming novel multi-core architectures
Real-time system compilers, operating systems and run-time systems
FPGAs and GPU-based accelerators
Novel accelerator-based architectures and architectural features
High-Level Abstractions and CAD tools for using accelerators
Neuro-Inspired Accelerators for Computing
Customized processor instruction sets
Compilers optimizing for dynamically reconfigurable processor arrays (DRPAs)
Case studies and challenges on DRPAs and accelerators
Power-efficient High-performance ICT and Data Centers
Supercomputing: compilers, operating systems, run time systems
Hardware-software interaction for low power high-performance
Modeling and analysis of energy costs for ICT subsystems and infrastructures
Power analysis for data centers, supercomputers, communication networks
Cross layer approaches and new paradigms for power efficiency in ICT
Power-efficient I/O interfaces and NoC design
Low power high performance in extreme scale supercomputing
Heterogeneous HPC by new storage technologies
Case studies: test cases, or design study challenges on data stations or supercomputers
Application-specific power efficiency by algorithmic and analytic efforts
Aplication of Computational Intelligence to implement high-performance systems (Neural Networks, Suport Vector Machines, Self-Organizing Maps, Neuromorphic systems)
Banking, financial modeling and financial database acceleration
Social networks, games, entertainment, ambient intelligence, ubiquitous and wearable computing
Bioinformatics, bio-inspired, medical, and genetics systems and life sciences
Physics and astronomy, weather prediction, oil and gas exploration.
Security systems, cryptography, object recognition and tracking, global navigation satellite systems
Audio/video, imaging, smart cameras, PDAs, smart image sensors, Reconfigurable Video Coding (RVC), etc. Aerospace, avionics, automotive and railway, and many other application areas
09月18日
2016
10月23日
2016
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