Testing of digital logic has made significant improvements in recent years with the use of the stuck-at and delay fault models. Advances in digital test have now led the way to analog and mixed-signal test, looking at analog fault modeling and coverage, testing of I/O interfaces and protocols, and also issues like power droop and crosstalk in digital logic. New data mining techniques such as outlier analysis and adaptive test have helped to improve quality by exploiting IC defects that have ‘analog’ signatures, even in digital devices. However, our capability for data analysis, defect modeling, simulation, and fault coverage of analog logic has not kept up with capabilities in the digital domain. All of this means that many of today’s biggest challenges in test are actually analog challenges, and product and test engineers are trying to discover issues that are often hidden within the volumes of “Big Data” in the TB/Hr to TB/Day range that needs to be processed and efficiently mined.s Besides presentations on "classical" digital product engineering, this year’s workshop is intended to focus on new, novel, and leading edge techniques that are being used for data analysis for analog circuits and designs, or for the analog behavior of digital logic. A list of suggested topics for papers and posters to be submitted for this workshop is provided below.