For high volume markets, bandgap voltage references may be viewed in a more favorable light due to the more stable and predictable VBE and VT that constitute the VBG. However, the majority of prior arts require passive resistors for bandgaps, which makes their implementation in small form factor, low-cost, and ultra low power applications, such as energy harvesting in wireless batteryless (WLBL) internet-of-things (IoT), impractical. Therefore, a resistorless CMOS bandgap is proposed that operates in the subthreshold mode and is suitable for such markets. The proposed bandgap reference size is preliminarily 180 um X 100 um in 0.18um digital CMOS. A composite active MOS resistor is proposed which has a small size and high resistance with acceptable matching characteristics, according to Monte Carlo (MC) simulations. Independently, the central bias and the bandgap loop circuitries apply PTAT voltages across functionally similar (composite active) MOS resistors, RM1i and RM1', to generate their respective operating currents, iM1i and iM1’, which track each other over fabrication process and temperature variations. As such, iM1i and iM1' can approximate a PTAT like behavior over temperature. Most importantly, the proposed active MOS resistor enable iM1i and iM1' to be mostly independent of VTH and chiefly a function of MOSFET's mobility, u, that is favored in manufacturing because u is more tightly controllable (compared to poly resistance or VTH, for example). WLBL IoT electronics, in general, may be subject to less orderly power supply patterns. To guard band against disorderly power supply and start-up patterns, the positive feedback loop associated with typical bandgap's PTAT amplifier (that is vulnerable to transients) is eliminated without denting bandgap's accuracy since it is compensated by design with iM1i and iM1' tracking each other. PMOS transistors are used in all of bandgap's key signal paths (i.e., amplifiers, composite MOS resistor, etc.,) which should enhance the design for manufacturability, provide some immunity against SOC's substrate (digital) jitters, and be less (1/f) noisy. The bandgap consumes about 220 nA of current. MC simulations indicates a typical TC of about ±7 ppm⁄°C over a 100°C temperature range is achievable, and a typical VC of about ±0.01% ⁄ V with 1.5V < VDD < 3.5V can be realized.