Analysis of the DC-link Capacitor Ripple Current for Neutral-Point-Clamped Three Level Inverter
编号:68 访问权限:仅限参会人 更新:2023-11-21 19:52:34 浏览:555次 口头报告

报告开始:2023年12月09日 11:30(Asia/Shanghai)

报告时间:15min

所在会场:[S2] Power electronic technology and application [S2] Power electronic technology and application

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摘要
This paper introduces 240-degree clamped pulse-width modulation strategy (240CPWM), traditional space vector modulation (SVPWM) and discontinuous pulse width modulation (DPWM1) for neutral-point-clamped three-level (NPC-3LI) inverters with a previa boost converter and provides a reasoned analysis of the capacitive ripple current with three PWM strategies and derives the calculation expressions. Using 240CPWM in inverters can greatly reduce switching losses, especially at a power factor of 1, which reduces switching losses by 85% and has nearly equal total harmonic distortion (THD) compared to SVPWM. In comparison, using 240-degree clamped pulse width modulation strategy can reduce the value of capacitive ripple current at full power factor, especially at high power factor, which will help reduce the volume on the DC side support capacitor.
关键词
neutral-point-clamped;PWM;three-level inverters;ripple
报告人
Xiaosa Sui
student Shanghai University

稿件作者
Xiaosa Sui Shanghai University
Deliang Wu Shanghai University
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重要日期
  • 会议日期

    12月08日

    2023

    12月10日

    2023

  • 11月01日 2023

    初稿截稿日期

  • 12月10日 2023

    注册截止日期

主办单位
IEEE IAS
承办单位
Southwest Jiaotong University (SWJTU)
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